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1/20 n 0.5msps to 50msps sampling frequency n 40mw @5msps, 150mw @ 50msps n 2.5v supply voltage with 2.5v/3.3v compati- bility for digital i/o n input range: 2vpp differential n sfdr up to 77db @ 50msps, fin=15mhz n enob up to10.5 bits @ 50msps, fin=15mhz n built-in reference voltage with external bias capability n pinout compatibility with tsa0801, tsa1001 and tsa1002 description the TSA1201 is a 12-bit, 50mhz maximum sampling frequency analog to digital converter using a cmos technology combining high performances and very low power consumption. the TSA1201 is based on a pipeline structure and digital error correction to provide excellent static linearity and achieve 10.5 effective bits at fs=50msps, and fin=15mhz, with a global power consumption of 150mw. the TSA1201 features adaptative behaviour to the application. its architecture allows to sample from 0.5msps up to 50msps, with a programmable power consumption which makes the application board even more optimized. it integrates a proprietary track-and-hold structure to ensure an high analog bandwidth of 1ghz and enable if-sampling. several features are available on the device. a voltage reference is integrated in the circuit. differential or single-ended analog inputs can be applied. the output data can be coded into two differential formats. a data ready signal is raised as the data is valid on the output and can be used for synchronization purposes. the TSA1201 is available in extended (-40c to +85c) temperature range, in small 48 pins tqfp package. applications n high speed data acquisition n medical imaging and ultrasound n portable instrumentation n high speed dsp interface n digital communication - if sampling order code pin connections (top view) package part number temperature range package c onditioning marking TSA1201if -40c to +85c tqfp48 tray sa1201i TSA1201ift -40c to +85c tqfp48 tape & reel sa1201i eval1201/aa evaluation board 7 x 7 mm tqfp48 vrefm vrefp d2 d3 d4 d5 d6 d7 d8 vinb agnd agnd index corner 13 14 15 16 17 18 19 20 21 22 47 1 2 3 4 5 6 7 8 9 10 11 12 23 24 32 31 30 29 28 27 26 25 33 35 34 36 48 44 43 42 41 40 39 38 37 46 45 agnd vin d9 d10 avcc avcc agnd ipol incm nc d0 (lsb) avcc dr src oeb agnd avcc dfsb vccbi gndbe nc nc vccbe gndbe gndbi dgnd dvcc clk dgnd vccbe nc or dgnd dvcc d11 (msb) d1 TSA1201 TSA1201 12-bit, 50msps, 150mw a/d converter march 2001
TSA1201 2/20 absolute maximum ratings operating conditions block diagram symbol parameter values unit av cc analog supply voltage 1) 0 to 3.3 v dv cc digital supply voltage 1) 0 to 3.3 v vccbi digital buffer supply voltage 1) 0 to 3.3 v vccbe digital buffer supply voltage 1) 0 to 3.6 v tstg storage temperature +150 c esd electrical static discharge - hbm - cdm-jedec standard 2 1.5 kv 1. all voltages values, except differential voltage, are with respect to network ground terminal. the magnitude of input and out put voltages must never exceed -0.3v or vcc+0v symbol parameter test conditions min typ max unit avcc analog supply voltage 2.25 2.5 2.7 v dvcc digital supply voltage 2.25 2.5 2.7 v vccbi internal (quiet) buffer supply voltage 2.25 2.5 2.7 v vccbe external (noisy) buffer supply voltage 2.25 2.5 3.5 v vrefp forced top voltage reference 0.8 - avcc v vrefm bottom internal reference voltage input 0 1 v stage stage stage 1 2 n reference timing circuit sequencer-phase shifting digital data correction buffers ipol vrefm vrefp clk +2.5v vin vinb dfsb oeb dr do to d11 or incm gnd gnda +2.5v/3.3v src
TSA1201 3/20 pin connections (top view) pin description vrefm vrefp d2 d3 d4 d5 d6 d7 d8 vinb agnd agnd index corner 13 14 15 16 17 18 19 20 21 22 47 1 2 3 4 5 6 7 8 9 10 11 12 23 24 32 31 30 29 28 27 26 25 33 35 34 36 48 44 43 42 41 40 39 38 37 46 45 agnd vin d9 d10 avcc avcc agnd ipol incm nc d0 (lsb) avcc dr src oeb agnd avcc dfsb vccbi gndbe nc nc vccbe gndbe gndbi dgnd dvcc clk dgnd vccbe nc or dgnd dvcc d11 (msb) d1 TSA1201 pin no name description observation pin no name description observation 1 ipol analog bias current input 25 d10 digital output cmos output (2.5v/3.3v) 2 vrefp top voltage reference 1v 26 d9 digital output cmos output (2.5v/3.3v) 3 vrefm bottom voltage reference 0v 27 d8 digital output cmos output (2.5v/3.3v) 4 agnd analog ground 0v 28 d7 digital output cmos output (2.5v/3.3v) 5 vin analog input 1vpp 29 d6 digital output cmos output (2.5v/3.3v) 6 agnd analog ground 0v 30 d5 digital output cmos output (2.5v/3.3v) 7 vinb inverted analog input 1vpp 31 d4 digital output cmos output (2.5v/3.3v) 8 agnd analog ground 0v 32 d3 digital output cmos output (2.5v/3.3v) 9 incm input common mode 0.5v 33 d2 digital output cmos output (2.5v/3.3v) 10 agnd analog ground 0v 34 d1 digital output cmos output (2.5v/3.3v) 11 avcc analog power supply 2.5v 35 d0(lsb) least significant bit output cmos output (2.5v/3.3v) 12 avcc analog power supply 2.5v 36 nc non connected 13 dvcc digital power supply 2.5v 37 nc non connected 14 dvcc digital power supply 2.5v 38 dr data ready output cmos output (2.5v/3.3v) 15 dgnd digital ground 0v 39 vccbe digital buffer power supply 2.5v/3.3v 16 clk clock input 2.5v compatible cmos input 40 gndbe digital buffer ground 0v 17 dgnd digital ground 0v 41 vccbi digital buffer power supply 2.5v 18 nc non connected 42 nc non connected 19 dgnd digital ground 0v 43 src slew rate control input 2.5v/3.3v cmos input 20 gndbi digital buffer ground 0v 44 oeb output enable input 2.5v/3.3v cmos input 21 gndbe digital buffer ground 0v 45 dfsb data format select input 2.5v/3.3v cmos input 22 vccbe digital buffer power supply 2.5v/3.3v 46 avcc analog power supply 2.5v 23 or out of range output cmos output (2.5v/3.3v) 47 avcc analog power supply 2.5v 24 d11(msb) most significant bit output cmos output (2.5v/3.3v) 48 agnd analog ground 0v
TSA1201 4/20 electrical characteristics avcc = dvcc = vccbe = vccbi = 2.5v,fs= 50msps,fin=2mhz, vin@ -1dbfs, vrefm=0v tamb = 25c (unless otherwise specified) timing characteristics timing diagram symbol parameter test conditions min typ max unit fs sampling frequency 0.5 50 mhz dc clock duty cycle 45 50 55 % tc1 clock pulse width (high) 9 10 ns tc2 clock pulse width (low) 9 10 ns to d data output delay (fall of clock to data valid) 6pf load capacitance 8ns tpd data pipeline delay 5.5 cycles to n falling edge of oeb to digital output valid data 1ns toff rising edge of oeb to digital output tri-state 1ns n-3 n-2 n-1 n+4 n+5 n n+3 n+1 n+2 n+6 n-3 n-1 n-4 n-5 n-6 n-7 n-8 n-9 clk oeb dr tod ton toff tpd + tod hz st ate n data out
TSA1201 5/20 conditions avcc = dvcc = vccbe = vccbi = 2.5v,fs= 50msps,fin=2mhz, vin@ -1dbfs, vrefm=0v tamb = 25c (unless otherwise specified) analog inputs reference voltage symbol parameter test conditions min typ max unit vin-vinb full scale reference voltage 2.0 vpp cin input capacitance 7.0 pf rin differential input resistance 5 m w bw analog input bandwitdh vin@full scale, fs=50msps 1000 mhz erb effective resolution bandwidth 1) 90 mhz 1. see parameters definition for more information. symbol parameter test conditions min typ max unit vrefp top internal reference voltage 0.79 1.0 1.16 v tmin= -40c to tmax= 85c 1) 0.79 1.16 v vpol analog bias voltage 1.08 1.15 1.22 v tmin= -40c to tmax= 85c 1) 1.07 1.23 v vincm input common mode voltage 0.40 0.55 0.65 v tmin= -40c to tmax= 85c 1) 0.4 0.65 v 1. not fully tested over the temperature range. guaranted by sampling.
TSA1201 6/20 conditions avcc = dvcc = vccbe = vccbi = 2.5v,fs= 50msps,fin=2mhz, vin@ -1dbfs, vrefp=1v, vrefm=0v tamb = 25c (unless otherwise specified) power consumption digital inputs and outputs symbol parameter test conditions min typ max unit pd power consumption in normal operation mode 1) 150 158 mw tmin= -40c to tmax= 85c 2) 165 mw icca analog supply current 1) 46 51 ma tmin= -40c to tmax= 85c 2) 55 ma iccd digital supply current 1) 1.9 2.2 ma tmin= -40c to tmax= 85c 2) 2.2 ma iccbi digital buffer supply current 1) 0.3 0.4 ma tmin= -40c to tmax= 85c 2) 0.4 ma iccbe digital buffer supply current 1) 9.8 10.8 ma tmin= -40c to tmax= 85c 2) 10.8 ma iccbez digital buffer supply current in high impedance mode 45ma rthja junction-ambient thermal resis- tance (tqfp48) 80 c/w 1. equivalent load: rload= 470 w and cload= 6pf 2. not fully tested over the temperature range. guaranted by sampling. symbol parameter test conditions min typ max unit clock input vil logic "0" voltage 0 0.8 v vih logic "1" voltage 2.0 2.5 v digital inputs vil logic "0" voltage 0 0.25 x vccbe v vih logic "1" voltage 0.75 x vccbe vccbe v digital outputs vol logic "0" voltage iol=10a 0 0.1 x vccbe v voh logic "1" voltage ioh=10a 0.9 x vccbe vccbe v ioz high impedance leakage current oeb set to vih -2.5 2.5 a c l output load capacitance 15 pf
TSA1201 7/20 conditions avcc = dvcc = vccbe = vccbi = 2.5v,fs= 50msps, vin@ -1dbfs, vrefp=1v, vrefm=0v tamb = 25c (unless otherwise specified) accuracy dynamic characteristics symbol parameter test conditions min typ max unit oe offset error fin= 2mhz, vin@+1dbfs 2.45 mv dnl differential non linearity fin= 2mhz, vin@+1dbfs 0.6 lsb inl integral non linearity fin= 2mhz, vin@+1dbfs 1.7 lsb - monotonicity and no missing codes guaranted symbol parameter test conditions min typ max unit sfdr spurious free dynamic range fin= 15mhz 1) -77.2 -68 dbc fin= 15mhz 2) -67 dbc snr signal to noise ratio fin= 15mhz 1) 61.6 64.9 db fin= 15mhz 2) 60.7 db thd total harmonics distorsion fin= 15mhz 1) -74.3 -68 db fin= 15mhz 2) -64 db sinad signal to noise and distorsion- ratio fin= 15mhz 1) 61 64.4 db fin= 15mhz 2) 60 db enob effective number of bits fin= 15mhz 1) 10 10.5 bits fin= 15mhz 2) 9.9 bits 1. equivalent load: rload= 470 w and cload= 6pf 2. tmin= -40c to tmax= 85c. not fully tested over the temperature range. guaranted by sampling.
TSA1201 8/20 definitions of specified parameters static parameters static measurements are performed through method of histograms on a 2mhz input signal, sampled at 50msps, which is high enough to fully characterize the test frequency response. the input level is +1dbfs to saturate the signal. differential non linearity (dnl) the average deviation of any output code width from the ideal code width of 1lsb. integral non linearity (inl) an ideal converter presents a transfer function as being the straight line from the starting code to the ending code. the inl is the deviation for each transition from this ideal curve. dynamic parameters dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 50msps. spurious free dynamic range (sfdr) the ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full nyquist band. it is expressed in dbc. total harmonic distortion (thd) the ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. it is expressed in db. signal to noise ratio (snr) the ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the nyquist band (f s /2) excluding dc, fundamental and the first five harmonics. snr is reported in db. signal to noise and distorsion ratio (sinad) similar ratio as for snr but including the harmonic distortion components in the noise figure (not dc signal). it is expressed in db. from the sinad, the effective number of bits (enob) can easily be deduced using the formula: sinad= 6.02 enob + 1.76 db. when the applied signal is not full scale (fs), but has an a 0 amplitude, the sinad expression becomes: sinad= 6.02 enob + 1.76 db + 20 log (2a 0 /fs) the enob is expressed in bits. analog input bandwidth the maximum analog input frequency at which the spectral response of a full power signal is reduced by 3db. higher values can be achieved with smaller input levels. effective resolution bandwidth (erb) the band of input signal frequencies that the adc is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the sinad is decreased by 3db or the enob by 1/2 bit. pipeline delay delay between the initial sample of the analog input and the availability of the corresponding digital data output,on the output bus. also called data latency. it is expressed as a number of clock cycles.
TSA1201 9/20 static parameter: integral non linearity fs=50msps; fin=1mhz; icca=45ma; n=131072pts static parameter: differential non linearity fs=50msps; fin=1mhz; icca=45ma; n=131072pts linearity vs. vcca fs=50msps; icca=45ma; fin=10mhz distortion vs. vcca fs=50msps; icca=45ma; fin=10mhz -3 -2 -1 0 1 2 3 0 500 1000 1500 2000 2500 3000 3500 4000 output code inl (lsbs) -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 output c ode dnl (lsbs) 62 62.5 63 63.5 64 64.5 65 65.5 66 66.5 67 2.25 2.35 2.45 2.55 2.65 vcca (v) dynamic parameters (db) 10 10.2 10.4 10.6 10.8 11 11.2 11.4 11.6 11.8 12 enob (bits) sinad enob snr -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 2.25 2.35 2.45 2.55 2.65 vcca (v) dynamic parameters (db) sfdr thd
TSA1201 10/20 linearity vs. vccd fs=50msps; icca=45ma; fin=10mhz linearity vs. vccbe fs=50msps; icca=45ma; fin=10mhz linearity vs. fs icca=45ma; fin=10mhz distortion vs. vccd fs=50msps; icca=45ma; fin=10mhz distortion vs. vccbe fs=50msps; icca=45ma; fin=10mhz distortion vs. fs icca=45ma; fin=10mhz 61 61.5 62 62.5 63 63.5 64 64.5 65 65.5 66 2.25 2.35 2.45 2.55 2.65 vccd (v) dynamic parameters (db) 10 10.2 10.4 10.6 10.8 11 11.2 11.4 11.6 11.8 12 enob (bits) sinad enob snr 60 61 62 63 64 65 66 2.25 2.35 2.45 2.55 2.65 vccbe (v) dynamic parameters (db) 10 10.2 10.4 10.6 10.8 11 11.2 11.4 11.6 11.8 12 enob (bits) sinad enob snr 50 52 54 56 58 60 62 64 66 68 70 15 25 35 45 55 65 75 fs (mhz) dynamic parameters (db ) 9.5 10 10.5 11 11.5 12 enob (bits) enob snr sinad -85 -83 -81 -79 -77 -75 -73 -71 2.25 2.35 2.45 2.55 2.65 vccd (v) dynamic parameters (db) thd sfdr -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 2.25 2.35 2.45 2.55 2.65 vccbe (v) dynamic parameters (db) sfdr thd -90 -85 -80 -75 -70 -65 -60 -55 -50 15 25 35 45 55 65 75 fs (mhz) dynamic parameters (db ) thd sfdr
TSA1201 11/20 linearity vs. fin fs=50mhz; icca=45ma linearity vs.temperature fs=49.7msps; icca=45ma; fin=15mhz distortion vs. fin fs=50mhz; icca=45ma distortion vs. temperature fs=49.7msps; icca=45ma; fin=15mhz single-tone 16k fft at 50msps fin=94.5mhz; icca=45ma, vin@-0.5dbfs 50 55 60 65 70 75 80 020406080 fin (mhz) dynamic parameters (db ) 7 7.5 8 8.5 9 9.5 10 10. 5 11 11. 5 12 enob snr sinad 55 57 59 61 63 65 67 69 -40 10 60 110 temperature (c) dynamic parameters (db ) 9.5 10 10. 5 11 11. 5 12 sinad enob snr -90 -85 -80 -75 -70 -65 -60 0 20406080 fin (mhz) dynamic parameters (db ) thd sfdr 50 55 60 65 70 75 80 85 90 -40 10 60 110 temperature (c) dynamic parameters (db ) sfdr thd 20 -140 0 -20 -40 -60 -80 -100 -120 15 10 5 0 power spectrum (db) frequency (mhz)
12/20 TSA1201 application note detailed information the TSA1201 is a high speed analog to digital converter based on a pipeline architecture and the latest deep submicron cmos process to achieve the best performances in terms of linearity and power consumption. the pipeline structure consists of 11 internal conversion stages in which the analog signal is fed and sequencially converted into digital data. each 10 first stages consists of an analog to digital converter, a digital to analog converter, a sample and hold and a gain of 2 amplifier. a 1.5-bit conversion resolution is achieved in each stage. the latest stage simply is a comparator. each resulting lsb-msb couple is then time shifted to recover from the delay caused by conversion. digital data correction completes the processing by recovering from the redundancy of the (lsb-msb) couple for each stage. the corrected data are outputed through the digital buffers. signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the clock. the advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. the highest dynamic performances are achieved while consumption remains at the lowest level. some functionalites have been added in order to simplify as much as possible the application board. these operational modes are described in the following table. the TSA1201 is pin to pin compatible with the 8bits/40msps tsa0801, the 10bits/25msps tsa1001 and the 10bits/50msps tsa1002. this ensures a conformity with the product family and above all, an easy upgrade of the application operational modes description data format select (dfsb) when set to low level (vil), the digital input dfsb provides a twos complement digital output msb. this can be of interest when performing some further signal processing. when set to high level (vih), dfsb provides a standard binary output coding. output enable (oeb) when set to low level (vil), all digital outputs remain active and are in low impedance state. when set to high level (vih), all digital outputs buffers are in high impedance state while the converter goes on sampling. when oeb is set to a low level again, the data are then present on the output with a very short ton delay. therefore, this allows the chip select of the device. the timing diagram summarizes this functionality. inputs outputs analog input differential level dfsb oeb src or dr most significant bit (msb) (vin-vinb) > range h l x h clk d11 -range > (vin-vinb) h l x h clk d11 range> (vin-vinb) >-range h l x l clk d11 (vin-vinb) > range l l x h clk d11 complemented -range > (vin-vinb) l l x h clk d11 complemented range> (vin-vinb) >-range l l x l clk d11 complemented x x h x hz hz hz x x x h x clk 25msps compliant slew rate x x x l x clk 50msps compliant slew rate
TSA1201 13/20 slew rate control (src) when set to high level (vih), all digital outputs currents are limited to a clamp value so that digital noise power is reduced to its minimum. rise and fall times just match 25mhz sampling rate assuming the load capacitance on each digital output remains below 10pf. when set to low level (vil), the maximum digital output current increases so that rise and fall times just match the 50mhz sampling rate assuming the load capacitance on each digital output remains below 10pf. out of range (or) this function is implemented on the output stage in order to set up an "out of range" flag whenever the digital data is over the full scale range. typically, there is a detection of all the data being at 0 or all the data being at 1. this ends up with an output signal or which is in low level state (vol) when the data stay within in the range, or in high level state (voh) when the data are out of the range. data ready (dr) the data ready output is an image of the clock being synchronized on the output data (d0 to d11). this is a very helpful signal that simplifes the synchronization of the measurement equipment or the controling dsp. as digital output, dr goes into high impedance state when oeb is asserted to high level as described in the timing diagram. driving the analog input differential inputs the TSA1201 has been designed to obtain optimum performances when being differentially driven. an rf transformer is a good way to achieve such performances. figure 1 describes the schematics. the input signal is fed to the primary of the transformer, while the secondary drives both adc inputs. the common mode voltage of the adc (incm) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.56v. it determines the dc component of the analog signal. as being an high impedance input, it acts as an i/o and can be externally driven to adjust this dc component. the incm is decoupled to maintain a low noise level on this node. our evaluation board is mounted with a 1:1 adt1-1 transformer from minicircuits. you might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. each analog input can drive a 1vpp amplitude input signal, so the resultant differential amplitude is 2vpp. figure 1 : differential input configuration single-ended input configuration some applications may require a single-ended input. this is easily achieved with the configuration reported on figure 2 for an ac-coupled input or on figure 3 and 4 for a dc-coupled input.. in the case of ac-coupled analog input, it is recommended to connect the other analog input to the common mode voltage of the circuit (incm) so as to properly bias the adc. the incm may remain at the same internal level (0.56v) thus driving only a 1vpp input amplitude, or it must be increased to 1v to drive a 2vpp input amplitude. figure 2 : ac-coupled single-ended input in the case of dc-coupled analog input, figure 3 shows the configuration for a 2vpp input signal. the dc component is driven by vrefp which is connected to incm and vinb and therefore imposes its voltage. vrefm being connected to ground, a dynamic of 2vpp is achievable. figure 4 describes the configuration for a 1vpp analog signal. in this case, vrefm is connected TSA1201 vin vinb incm 50 w 100pf 330pf 470nf 10nf analog source 1:1 adt1-1 TSA1201 vin vinb incm 50 w 100nf 330pf 470nf 10nf signal source 1v
TSA1201 14/20 to vinb and incm. the latest imposes its voltage. vrefp being internally set to 1v, the dynamic is then 1vpp. figure 3 : dc-coupled 2vpp analog input figure 4 : dc-coupled 1vpp analog input if-sampling software radio has become a common mode for receiving data through rf receivers. its main advantage being to digitally implement what was originally done with analog functions such as discriminators, demodulation and filtering. originally, bipolar process was mainly used because they provided high transistor transit frequency, while pure cmos technology showed a lower one. with new cmos process and circuit topology, higher frequencies are now achieved. the TSA1201 has been specifically designed to meet the requirement of sampling at intermediate frequency. for this purpose, the track-and-hold of the first pipeline stage has been built to ensure the global linearity of the overall adc to perform the right characteristics. our proprietary track-and-hold has a patented switch control system to enable the performances not to be degraded as input signal frequency increases. as a result, an analog bandwidth of 1ghz is achieved. reference connection internal reference in the standard configuration, the adc is biased with the internal reference voltage. vrefm pin is connected to analog ground while vrefp is internally set to a voltage of 1.0v. it is recommended to decouple the vrefp in order to minimize low and high frequency noise. refer to figure 5 for the schematics. figure 5 : internal reference setting external reference it is possible to use an external reference voltage instead of the internal one for specific applications requiring even better linearity or enhanced temperature behaviour. in this case, the amplitude of the external voltage must be at least equal to the internal one (1.0v). using the stmicroelectronics vref ts821 leads to optimum performances when configured as shown on figure 6. figure 6 : external reference setting this can be very helpful for example for multichannel application to keep a good matching over the sampling frequency range. TSA1201 vin vinb incm 330pf 470nf 10nf analog dc analog+dc vrefp vrefm TSA1201 vin vinb incm 330pf 470nf 10nf analog dc analog+dc vrefm TSA1201 vi n vinb vrefm 1.0v vrefp 330pf 470nf 10nf 1k w TSA1201 vi n vinb vrefm vrefp external reference ts821 vcca 330pf 470nf 10nf
TSA1201 15/20 clock input the quality of your converter is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. the duty cycle must be between 45% and 55%. the clock power supplies must be separated from the adc output ones to avoid digital noise modulation at the output. it is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5msps, before applying the supply voltages. power consumption optimization the internal architecture of the TSA1201 enables to optimize the power consumption according to the sampling frequency of. for this purpose, a resistor is placed between ipol and the analog ground pins. therefore, the total dissipation is adjustable from 0.5msps up to 50msps. this feature is of highest importance when power saving conditions the application. the TSA1201 will combine highest performances and lowest consumption at 50msps when rpol is equal to 12k w . at lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. as an example, 40mw total power consumption is achieved at 5 msps with rpol equal to 190k w and 35mw is dissipated at 1msps with rpol equal to 350k w . the table below sums up the relevant data. figure 7 describes the behaviour of the converter as sampling frequency increases and shows the optimum in terms of analog current and polarization resistor. total power consumption optimization depending on rpol value figure 7 : optimized power consumption fin=1mhz layout precautions to use the adc circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - first of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the pcb is mandatory for high speed circuit applications to provide low inductance and low resistance common return. the separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. - power supply bypass capacitors must be placed as close as possible to the ic pins in order to improve high frequency bypassing and reduce harmonic distortion. - proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. all leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - to keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. to minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - choose component sizes as small as possible (smd). fs (msps) 5 35 50 rpol ( k w) 190 29 12 optimized power (mw) 40 100 150 0 20 40 60 80 100 120 140 160 180 200 5 25456585 fs(mhz) rpol(kohms) 0 10 20 30 40 50 60 70 icca(ma) rpol i cca
TSA1201 16/20 eval1201 evaluation board the characterization of the board has been made with a fully adc devoted test bench as shown on figure 8. the analog signal must be filtered to be very pure. the dataready signal is the acquisition clock of the logic analyzer. the adc digital outputs are latched by the octal buffers 74lcx573. all characterization measurements have been made with: - sfsr=+0.5db for static parameters. - sfsr=-0.5db for dynamic parameters. figure 8 : analog to digital converter characterization bench sine wave generator power sine wave generator adc evaluation board logic analyzer pulse generator dataready data ck vin hp8644b hp8644b hp8133a tla704
TSA1201 17/20 figure 9 : TSA1201 evaluation board schematic r1 50 r2 1k r3 50 c1 100pf c2 330pf c3 470nf c4 10nf c5 330pf c6 10nf c7 470nf c8 330pf c9 10nf c10 470nf c11 330pf c12 10nf c13 470nf c14 330pf c15 10nf c16 470nf raj1 47k c17 330pf c18 10nf c19 470nf j4 clj/smb c24 10 oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u2 74lcx573 oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u3 74lcx573 r10 47k r11 47k r12 47k r14 47k r15 47k c25 330pf c27 10nf c28 470nf + c29 10f do d7 d8 d9 d10 d11 d12 r13 47k c30 330pf c31 10nf c32 470nf 1 2 12 a vcc 1 2 j17 vddbuff3v 1 2 j18 vccb1 + c34 47 + c35 47 1 2 2 v refp 1 2 5 v refm 1 2 7 r egl com mode 1 2 8 m es com mode avcc avcc vccb1 vccb1 1 2 j9 dfsb 1 2 j10 oeb 1 2 j11 1 2 j13 c26 330pf c39 10nf c37 470nf vccb2 c33 330pf c40 10nf c38 470nf d13 1 2 19 a gnd 1 2 2 0 d gnd 1 2 2 1 g ndb2 1 2 2 2 g ndb1 c41 10f + c42 47f ipol 1 vrefp 2 vrefm 3 agnd 4 vin 5 agnd 6 vinb 7 agnd 8 incm 9 agnd 10 avcc 11 avcc 12 dvcc 13 dvcc 14 dgnd 15 clk 16 dgnd 17 nc 18 dgnd 19 gndbuff 20 gndbuff 21 2.5vccbuff 22 or 23 d13 24 d12 25 d11 26 d10 27 d9 28 d8 29 d7 30 d6 31 d5 32 d4 33 d3 34 d2 35 d1 36 d0 37 dr 38 2.5vccbuff 39 gndbuff 40 2.5vccbuff 41 nc 42 nc 43 oeb 44 dfsb 45 avcc 46 avcc 47 agnd 48 8-14bits adc tsa1002 or r16 47k r17 47k r18 47k r19 47k d1 d2 d3 d4 d5 d6 dr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 j6 32pin 1 2 j16 con2 c20 330pf c21 10nf c22 470nf c23 10 1 2 j15 dvcc + c36 47 1 4 3 2 6 t1 t2-at1-1wt 1 4 3 2 6 t2 t2-at1-1wt TSA1201 r1 50 r2 1k r3 50 c1 100pf c2 330pf c3 470nf c4 10nf c5 330pf c6 10nf c7 470nf c8 330pf c9 10nf c10 470nf c11 330pf c12 10nf c13 470nf c14 330pf c15 10nf c16 470nf raj1 47k c17 330pf c18 10nf c19 470nf j4 clj/smb c24 10 oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u2 74lcx573 oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u3 74lcx573 r10 47k r11 47k r12 47k r14 47k r15 47k c25 330pf c27 10nf c28 470nf + c29 10f do d7 d8 d9 d10 d11 d12 r13 47k c30 330pf c31 10nf c32 470nf 1 2 12 a vcc 1 2 j17 vddbuff3v 1 2 j18 vccb1 + c34 47 + c35 47 1 2 2 v refp 1 2 5 v refm 1 2 7 r egl com mode 1 2 8 m es com mode avcc avcc vccb1 vccb1 1 2 j9 dfsb 1 2 j10 oeb 1 2 j11 1 2 j13 c26 330pf c39 10nf c37 470nf vccb2 c33 330pf c40 10nf c38 470nf d13 1 2 19 a gnd 1 2 2 0 d gnd 1 2 2 1 g ndb2 1 2 2 2 g ndb1 c41 10f + c42 47f ipol 1 vrefp 2 vrefm 3 agnd 4 vin 5 agnd 6 vinb 7 agnd 8 incm 9 agnd 10 avcc 11 avcc 12 dvcc 13 dvcc 14 dgnd 15 clk 16 dgnd 17 nc 18 dgnd 19 gndbuff 20 gndbuff 21 2.5vccbuff 22 or 23 d13 24 d12 25 d11 26 d10 27 d9 28 d8 29 d7 30 d6 31 d5 32 d4 33 d3 34 d2 35 d1 36 d0 37 dr 38 2.5vccbuff 39 gndbuff 40 2.5vccbuff 41 nc 42 nc 43 oeb 44 dfsb 45 avcc 46 avcc 47 agnd 48 8-14bits adc tsa1002 or r16 47k r17 47k r18 47k r19 47k d1 d2 d3 d4 d5 d6 dr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 j6 32pin 1 2 j16 con2 c20 330pf c21 10nf c22 470nf c23 10 1 2 j15 dvcc + c36 47 1 4 3 2 6 t1 t2-at1-1wt 1 4 3 2 6 t2 t2-at1-1wt TSA1201
TSA1201 18/20 figure 10 : printed circuit of evaluation board. printed circuit board - list of components p art des ign fo otprint part des ign fo otprint part des ign foo tprint p art des ign fo o tprint type ato r type ato r type ator type ato r 10 u f c 2 4 12 10 330pf c33 603 470nf c7 805 avcc j12 fiche2mm 10 u f c 2 3 12 10 330pf c20 603 470nf c16 805 clj/smb j4 smb/h 10 u f c 4 1 12 10 330pf c8 603 470nf c19 805 agnd j19 fiche2mm 10 u f c 2 9 12 10 330pf c2 603 470nf c3 805 dfsb j9 fiche2mm 100pf c1 603 330pf c5 603 47k w r12 603 dgnd j20 fiche2mm 10nf c12 603 330pf c11 603 47k w r14 603 dvcc j15 fiche2mm 10nf c39 603 330pf c30 603 47k w r11 603 gndb1 j22 fiche2mm 10nf c15 603 330pf c17 603 47k w raj1 vr5 gndb2 j21 fiche2mm 10nf c40 603 330pf c14 603 47k w r10 603 mes co m mo de j8 fiche2mm 10nf c27 603 47uf c36 cap 47k w r19 603 oeb j10 fiche2mm 10nf c4 603 47uf c34 cap 47k w r13 603 regl co m mode j7 fiche2mm 10nf c21 603 47uf c35 cap 47k w r15 603 t2-at1-1wt t2 adt 10nf c31 603 47uf c42 cap 47k w r16 603 t2-at1-1wt t1 adt 10nf c6 603 470nf c22 805 47k w r17 603 vccb1 j18 fiche2mm 10nf c9 603 470nf c32 805 47k w r18 603 vddbuff3v j17 fiche2mm 10nf c18 603 470nf c37 805 50 w r3 603 vin j1 smb/h 1k w r2 603 470nf c38 805 50 w r1 603 vrefm j5 fiche2mm 32p in j6 idc32 470nf c13 805 74lcx573 u3 tssop 20 vrefp j2 fiche2mm 330pf c25 603 470nf c28 805 74lcx573 u2 tssop 20 tsa1002 u1 tqfp 48 330pf c26 603 470nf c10 805 con2 j16 sip2 TSA1201 p art des ign fo otprint part des ign fo otprint part des ign foo tprint p art des ign fo o tprint type ato r type ato r type ator type ato r 10 u f c 2 4 12 10 330pf c33 603 470nf c7 805 avcc j12 fiche2mm 10 u f c 2 3 12 10 330pf c20 603 470nf c16 805 clj/smb j4 smb/h 10 u f c 4 1 12 10 330pf c8 603 470nf c19 805 agnd j19 fiche2mm 10 u f c 2 9 12 10 330pf c2 603 470nf c3 805 dfsb j9 fiche2mm 100pf c1 603 330pf c5 603 47k w r12 603 dgnd j20 fiche2mm 10nf c12 603 330pf c11 603 47k w r14 603 dvcc j15 fiche2mm 10nf c39 603 330pf c30 603 47k w r11 603 gndb1 j22 fiche2mm 10nf c15 603 330pf c17 603 47k w raj1 vr5 gndb2 j21 fiche2mm 10nf c40 603 330pf c14 603 47k w r10 603 mes co m mo de j8 fiche2mm 10nf c27 603 47uf c36 cap 47k w r19 603 oeb j10 fiche2mm 10nf c4 603 47uf c34 cap 47k w r13 603 regl co m mode j7 fiche2mm 10nf c21 603 47uf c35 cap 47k w r15 603 t2-at1-1wt t2 adt 10nf c31 603 47uf c42 cap 47k w r16 603 t2-at1-1wt t1 adt 10nf c6 603 470nf c22 805 47k w r17 603 vccb1 j18 fiche2mm 10nf c9 603 470nf c32 805 47k w r18 603 vddbuff3v j17 fiche2mm 10nf c18 603 470nf c37 805 50 w r3 603 vin j1 smb/h 1k w r2 603 470nf c38 805 50 w r1 603 vrefm j5 fiche2mm 32p in j6 idc32 470nf c13 805 74lcx573 u3 tssop 20 vrefp j2 fiche2mm 330pf c25 603 470nf c28 805 74lcx573 u2 tssop 20 tsa1002 u1 tqfp 48 330pf c26 603 470nf c10 805 con2 j16 sip2 TSA1201
TSA1201 19/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in france - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com package mechanical data 48 pins - plastic package dim. millimeters inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 d3 5.50 0.216 e 0.50 0.0197 e 9.00 0.354 e1 7.00 0.276 e3 5.50 0.216 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 7 (max.) 48 37 d3 e 13 24 1 12 25 36 c a1 a2 a d1 d e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane b
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